1. Field of the Invention
The present invention relates in general to an insulated gate field effect semiconductor device and method of manufacturing the same.
2. Description of the Prior Art
A variety of approaches have been carried out in order to miniaturize integrated circuits and achieve a higher packing density in a chip. Particularly, remarkable advances have been reported in the development of the technology to miniaturize insulated gate field effect semiconductor devices, denoted as MOSFET for short. MOS is the acronym of Metal Oxide Semiconductor. The metal used in MOSFETs generally includes, in addition to genuine metals, conductive materials such as semiconductors having a sufficient conductivity, alloys composed of semiconductor(s) and/or metal(s). The oxide generally includes, in addition to genuine oxides, insulating materials having a sufficient resistivity such as nitrides. Although these materials do exactly not correspond to the acronym MOS, the term MOSFET is used in the broad sense in this description.
The miniaturizing of MOSFETs is realized by decreasing the width of the gate electrode. The decrease of the width of the gate electrode leads to the decrease of the channel length underlying the gate electrode. This also results in a high operational speed because the short channel length decreases the time required for carriers to pass across the channel.
The miniaturizing, on the other hand, gives rise to other problems, i.e. short channel effects. One of the most serious problems thereof is hot electron effects. In the structure comprising highly doped source and drain regions with an inversely doped intervening channel region therebetween, the strength of the electric field at the boundary between the channel region and the highly doped region increases as the channel length decreases. As a result, the characteristics of the device are unstable.
The LDD (lightly-doped-drain) structure has been proposed to solve the above problem. This structure is schematically illustrated in FIG. 1(D). In the figure, reference numeral 207. designates a lightly doped region formed inside of a highly doped region 206. The region 207 is called a LDD region. By provision of such a LDD region, the strength of the electric field in the vicinity of the boundary between the channel region and the drain region is decreased so that the operation of the device becomes more stable.
FIGS. 1(A) to 1(D) are cross sectional views showing a method of making a conventional MOSFET. Although an n-channel transistor is explained here, a p-channel transistor is formed in the same manner only by inverting the conductivity type. A semiconductor film is deposited onto an insulating substrate and patterned in order to define a semiconductor active region. An oxide film and a conductive film are deposited on the semiconductor film and patterned by etching in order to form a gate electrode 201 insulated by a gate insulating film 202. With the gate electrode 201 and the insulating film 202 as a mask, lightly doped regions 203 are formed by ion implantation in a self-aligning manner.
Next, the structure is coated with an insulating film 204 such as a PSG film. The insulating film 204 is removed by an anisotropic etching (directional etching) leaving spacers 205 flanking the gate electrode 201. With the spacers 205 as a mask, heavily doped regions 206 are formed to provide source and drain regions. By employing this LDD design, the channel length can be decreased to as short as 0.1 micrometer while the channel length in usual designs can not be decreased to 0.5 micrometer or shorter.
The problems associated with the short channel designs, however, are not completely solved by this technique. Another problem is the resistance of the gate electrode which has become narrow. Even if the switching speed of the device is increased by the short channel, the speed-up may possibly come to naught due to propagation delay along the high resistant gate electrode. The resistance of the gate electrode can be decreased to some extent by employing a metal silicide having a low resistivity in place of polysilicon to form the gate electrode or by providing a low resistant line such as an aluminum line extending along the gate electrode. These techniques, however, can not solve the high resistance problem when the width of the gate electrode is no larger than 0.3 micrometer.
Another approach to solve the problem is to increase the aspect ratio of the gate electrode, i.e. the ratio of the height to the width of the gate electrode. The resistance of the gate electrode decreases in proportion to the cross sectional area which increases as the aspect ratio increases. From the view point of manufacture restraints, the aspect ratio can not be increased so much. This is mainly because the width of the spacers depend on the height of the gate electrode. The spacer is formed with its width of 20% or wider of the height of the gate electrode. Accordingly if 0.1 micrometer width L (FIG. 1(D)) is desired, the height of the gate electrode can not exceed 0.5 micrometer. If the gate electrode has a height exceeding 0.5 micrometer, the width L exceeds 0.1 micrometer resulting in a higher resistance between the source and drain regions.
In the case of 0.5 micrometer height (h), 1.0 micrometer width (W) and 0.1 micrometer width (L) in FIG. 1(D), if the width (W) of the gate electrode is desired to be decreased to 0.5 micrometer, the height of the electrode must be increase to 1.0 micrometer in order to avoid increase of the gate resistance. The width (L) of the spacers, however, becomes 0.2 micrometer so that the resistance between the source and drain regions is doubled. The halved channel length is expected to improve double the operational speed. The increase of double the source and drain resistance, however, cancels the improvement. Accordingly, the. operational speed remains same as achieved before the shrinkage in size.
Usually, the width of the spacer becomes as wide as 50% to 100% of the height of the gate electrode, which width provides a further severe condition. The aspect ratios of the gate electrodes, therefore, have been no higher than 1, or in many cases no higher than 0.2 in accordance with the conventional LDD technique. In addition to this, the width of the spacer has been substantially dispersed, due to expected variations of production, which results in dispersed characteristics of the products. The conventional LDD technique has brought high integrations and high speeds and, on the contrary, impeded further improvement.
On the other hand, recently, semiconductor integrated circuits have been formed within semiconductor thin films deposited on insulating substrates such as glass substrates (e.g., in the case of liquid crystal displays and image sensors) or on single crystal semiconductor substrates coated with insulating films (e.g., in the case of three-dimensional ICs). The LDD technique is often effective also in these cases. Because of disparity of thickness of one PSG film formed over a large glass substrate, the sizes of spacers become different depending upon the positions of the substrate.
In the case of LDD designs to be formed on an insulating surface for three-dimensional ICs, if there have been formed other circuits under the surface, the surface is usually not even so that the sizes of spacers are substantially dispersed. The yield of the conventional productions of three-dimensional ICs has therefore been low with dispersed characteristics.
It is an object of the present invention to provide a method of manufacturing an insulated gate field effect semiconductor device within a small area which has a high switching speed and a low on-state resistance.
It is another object of the present invention to provide a method of manufacturing an insulated gate field effect semiconductor device having LDD regions which are short as compared with the height of the gate electrode.
It is a further object of the present invention to provide an insulated gate field effect semiconductor device having a new structure equivalent to LDD regions.
Additional objects, advantages and novel features of the present invention will be set forth in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the present invention. The object and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
To achieve the foregoing and other object, and in accordance with the present invention, as embodied and broadly described herein, an insulated gate field effect semiconductor device is manufactured by the steps of forming a conductive pattern on a semiconductor substrate through a gate insulating film, introducing an impurity into the semiconductor substrate with the conductive pattern as a mask, oxidizing an external surface of the conductive pattern to leave a gate electrode therein, and introducing an impurity into the semiconductor substrate with the oxidized conductive pattern as a mask.
The oxidation of the external surface of the conductive pattern can be carried out by anodic oxidation, a plasma oxidation (vapor phase oxidation) or a liquid phase oxidation. A bias voltage is applied to the conductive pattern or a lead connected thereto in the plasma oxidation or the liquid phase oxidation.
The present invention will be briefly explained with reference to FIGS. 2(A) to 2(C). Although an n-channel transistor is explained here, a p-channel transistor is formed in the same manner. A p-type silicon semiconductor thin film is deposited onto an insulating substrate and patterned in order to define a semiconductor active region. An oxide film and a conductive film are deposited on the semiconductor film and patterned by etching in order to form a conductive film 101 insulated by a gate insulating film 102 as illustrated in FIG. 2(A). The conductive film is made of, for example, titanium (Ti), aluminum (Al), tantalum (Ta), chromium (Cr) or an alloy consisting of two or more of these metals. With the gate electrode 101 and the insulating film 102 as a mask, lightly doped regions 103 are formed by ion implantation in a self-aligning manner. The doping concentration of the regions 103 is 1xc3x971017 to 5xc3x971018 cmxe2x88x923.
Next, the upper and side surfaces of the conductive film 101 are anodic oxidized to form a gate electrode 105 and an insulating oxide film 104 as illustrated in FIG. 2(B). The size of the gate electrode 105 is smaller than the size of the conductive film 101 because the surface portion of the film 101 is eaten by the oxidation to form the oxide film 104. Thickness of the oxide film 104 is preferably 200 to 3500 xc3x85, more preferably 1000 to 2500 xc3x85. The spacial relationship between the gate electrode 105 and the lightly doped regions 103 is very important. If there is a substantial area of the channel region which is not covered by the overlying gate electrode, the channel region might not form a sufficiently effective channel therein when the gate electrode is given a signal. On the contrary, if the gate electrode overlaps the lightly doped regions 103 too much, a substantial parasitic capacitance is formed resulting in a slow switching speed.
It is, however, not so difficult in accordance with the present invention to control the relationship. The spread of the dopant within the lightly doped regions 103 due to secondary scattering of the ion implantation can be controlled by adjusting the acceleration energy of ions. The shrinkage of the conductive film 101 due to the anodic oxidation is also controlled by adjusting the thickness of the oxide film, i.e. by adjusting the oxidation condition. The thickness of the oxide film 104 can be controlled within xc2x110 nm from a target thickness. The secondary scattering can be controlled at the same order accuracy. Namely, by accurately designing the respective dimensions, the optimum relationship between the lightly doped regions 103 and the gate electrode 105 can be achieved only with an error as small as 10 nm.
With the oxide film 104 as a mask, heavily doped regions 106 are formed by ion implantation to provide source and drain regions in accordance with self-aligning configuration as illustrated in FIG. 2(C). The doping concentration of the heavily doped regions 106 is 1xc3x971020 to 5xc3x971021 cmxe2x88x923. The inner portions of the lightly doped regions 103 is left as LDD structures 107 having same configuration and same function as a conventional LDD structure. The width L of the LDD regions is, however, determined by the thickness of the oxide film 104 but independent of the height of the gate electrode so that the aspect ratio of the gate electrode can be increased to exceed 1.
In accordance with the present invention, the width L of the LDD regions can be arbitrarily and finely adjusted from 10 nm to 0.1 micrometer. The overlapping dimension between the gate electrode 105 the LDD regions 107 can be controlled at a similar accuracy as explained above. The channel length W can be reduced to 0.5 micrometer or less in this case. Conventionally, it had been very difficult to form a LDD region having 100 nm or less width and the error had been usually 20% or thereabout. It becomes, however, possible to form LDD regions having 10 to 100 nm widths only with errors of about 10%.
Furthermore, in accordance with the present invention, the process is simplified because an insulating film need not be formed over the gate electrode in order to form spacers. The oxide film 104 formed by anodic oxidation is extremely uniform over the gate electrode and has a high resistivity. The formation of the oxide film can be carried out in the same manner wherever it is located on an uneven substrate.
The LDD structure 107 illustrated in FIG. 2(C) is same as that of the prior art LDD technique. A similar function can be realized by utilizing noncrystalline semiconductors such as amorphous or semiamorphous semiconductors. In such a case, the LDD regions 107 are composed of a noncrystal semiconductor material doped with an impurity while the heavily doped regions 106 are composed of an usual single crystalline or polycrystalline impurity semiconductor. The LDD regions and the heavily doped region may have the same doping concentration in this case. An appropriate terminator such as hydrogen or a halogen has to be introduced into the noncrystal semiconductor material in order to terminate dangling bonds occurring in the material. FIG. 3(D) illustrates an example of a MOSFET having such a LDD structure. The inventor discovered that this new type device utilizing a noncrystal semiconductor material exhibited improvement of characteristics of TFTs in the same manner as conventional LDD devices.
FIG. 4(A) is a graph showing the relationship between the gate voltage Vg and the drain current Id. Curve A is plotted in the case of the new type MOSFET device utilizing a noncrystal semiconductor. Curve B is plotted in the case of a conventional FET device with no LDD structure. In the case of the conventional device, the drain current increases also when xe2x88x92Vg increases. This undesirable characteristic is called reverse current leakage. When complementary FETs are formed, this is serious problem.
Contrary to this, the characteristic is improved by forming the noncrystal semiconductor regions as seen from curve A. The mechanism of the improvement has not certainly been understood yet. One assumption is thought that the effective doping concentration of the noncrystal region is lower than the actual doping concentration because the ionization rate in the noncrystal region is lower than that in the crystal region. For example, the ionization rate of amorphous silicon is 0.1 to 10% while that of single crystalline or polycrystalline silicon is approximately 100%.
Another assumption is based upon difference between the noncrystal and the crystal in band-gap. FIG. 4(B) illustrates the energy band structure of a semiconductor device with a LDD structure when no gate signal is supplied. FIG. 4(C) illustrates the energy band structure of a semiconductor device with a LDD structure when a large gate voltage is supplied in the reverse direction. In this case, small carrier leakage takes place through the device due to tunnel effects and hopping among trapping levels existing in the band-gap. The provision of the LDD structure is effective to increase the band-gap at the junctions so that the carrier leakage is suppressed as compared with a device having no LDD structure. The improvement due to the LDD structure is particularly remarkable when the FET is a thin film transistor (TFT) because a TFT utilizes a nonuniform semiconductor material such as polysilicon forming trapping levels therein which are considered to originate from grain boundaries.
The reverse current leakage is furthermore suppressed by increasing the band-gap of the LDD regions. FIG. 4(D) illustrates the energy band structure of a semiconductor device with LDD regions having wide band-gaps when no gate signal is supplied. FIG. 4(E) illustrates the energy band structure of the same semiconductor device when a large gate voltage is supplied in the reverse direction. As shown in the figures, the band-gaps at the LDD regions are substantially increased as compared with the case shown in FIGS. 4(B) and 4(C). The probability of tunnel current through the LDD regions quickly decreases as the band-gap (barrier) increases. The hopping through local levels in the band-gap is also decreased by increasing the band-gap because the mechanism of hopping is also based upon combinational tunnel effects. For this reason, LDD structure having a wide band-gap is advantageous with respect to improvement of FET characteristics. In this sense, noncrystal semiconductor materials, e.g. amorphous silicon having 1.8 eV band-gap is considered to be useful for forming an equivalent structure whereas the band-gap of polysilicon is 1.1 eV.
The band-gap is increased also by introducing other suitable impurities such as carbon, nitrogen, oxygen and so forth into silicon semiconductors at appropriate stoichiometrical or non-stoichiometrical ratios in order to obtain the same effects. The impurities such as carbon, nitrogen, oxygen are not so desirable for silicon semiconductors so that low densities thereof is favorable in general. In accordance with the present invention, no such impurities are utilized. The densities of such impurities are desirably reduced to 7xc3x971019 cmxe2x88x923 or less in the following embodiments in order to make excellent devices.